This invention relates to circuits for electro-over-stress (EOS) protection, and more particularly for improving internal electro-static-discharge (ESD) protection using external components.
Significant advances in semiconductor process technology have produced extremely small transistors. These tiny transistors have thin oxide and insulating layers that can easily be damaged by relatively small currents with even a moderate driving force (voltage). Special care is required when a person handles these semiconductor devices.
Static electricity that normally builds up on a person can discharge across the input pins or a semiconductor integrated circuit (IC or chip). IC chips are routinely tested for resistance to such electro-static-discharges (ESD) using automated testers that apply a voltage across different pairs of pins of the chip. Any pair of pins may be chosen for the ESD test.
FIG. 1 shows a prior-art integrated circuit (IC) chip being tested with an ESD pulse. Chip 10 contains complementary metal-oxide-semiconductor (CMOS) transistors such as transistor 12 that is coupled between input pin A and output pin B, which are some of pins 14 of chip 10. During normal operation, a power supply voltage is applied to Vcc pin 16, and a ground supply is applied to ground pin 18.
To protect inputs from ESD pulses, protection diodes are often added to each input pin of chip 10. Protection diode 20 turns on when the input voltage is sufficiently above or below the ground voltage. Diodes can be formed using diffusion regions or well regions in the semiconductor substrate.
Diode 20 is reverse biased and off during normal operation with typical power-supply and ground voltages. However, when a positive ESD pulse is applied between pin A and ground, the voltage is larger than the reverse-bias turn-on voltage for diode 20, and diode 20 conducts current in the reverse direction. When a negative ESD pulse is applied across pins A and ground, diode 20 is forward biased and conducts a large current.
Diode 20 is designed to pass industry-standard ESD tests. These tests generate ESD pulses based on models such as the ESD machine model, which creates the ESD pulse by discharging a 200-pF capacitor that was charged to 100-400 volts, or the ESD human-body model, which creates the ESD pulse by discharging a 100-pF capacitor that was charged to 1000-4000 volts. The human-body model discharges the capacitor through a 1.5 k-ohm resistor, which limits the peak current in the pulse but extends the duration of the pulse.
Since the current of both the ESD human model and the machine model are discharged from a small 100 or 200 pF capacitor, the duration of the discharged current is very short.
When the positive ESD high voltage pulse applied to pin A, diode 20 will break over around +14.7V and current is discharged from the 100 pf or 200 pF capacitor (of the ESD human body model or machine to ground connected to pin 18. Meanwhile the voltage applied to transistor 12 connected to pin A is limited to 14.7V. Transistor 12 can tolerate xcex114.7V and therefore is protected.
When a negative ESD high voltage pulse is applied to pin A diode 20 is forward biased relative to ground pin 18 at xe2x88x920.7V (at 10 ma) to xe2x88x923.3V (at 500 ma). Diode 20 can tolerate a xe2x88x92500 ma forward-bias current at xe2x88x923.3 volt without damage. Therefore, diode 20 is vulnerable when a positive ESD voltage pulse is applied to one of pins 14.
Diode 20 can tolerate the standard ESD human model/machine model and the short discharge current duration, at both positive and negative directions without being damaged. Diode 20 can tolerate this standard ESD voltage repeatedly and operates properly after stress.
Diode 20 can be burned out by electro-over-stress (EOS) pulses that are low voltage but higher current (100 ma above) with long duration. These kinds of pulses can be generated in real-world hot-swap interfaces for telecom and datacom applications.
FIG. 2 highlights a telecom hot-swap application that has caused ESD-diode failures. Diode 20 has been observed to have burned out in some hot-swap telecommunications applications. In the hot-swap application, chip 10 is mounted on a removable printed-circuit board (PCB) 94. When removable board 94 is plugged into backplane bus connector 90, sparks are sometimes seen, since the backplane bus board 92 remains powered up during insertion of removable board 94.
Telecom and datacom applications can use a large power-supply voltage of 48 volts in the backplane bus. DCxe2x80x94DC couplers 80, 81 are used on removable board 94 and on backplane board 92 to isolate the power-supply and ground voltages on different boards. There is a common ground pin 103 between the backplane ground bus and removable board 94 ground bus. However, before common ground pin 103 is connected during insertion, there is no common ground yet, and the DC voltage could be +48 to xe2x88x9248 volts relative to ground pin 18 of chip 10. DC coupler 80 can be a transformer that steps the 48-volt input down to a 5-volt supply to chip 10.
Various parasitic resistances, capacitances, and inductances 82 exist on removable board 94 that can couple some of the 48-volt power-supply voltage to pins of chip 10. Although the 48-volt supply is stepped down to 5 volts to power bus 42 and Vcc pin 16, some coupling of the 48-volt backplane supply can occur on ground bus 44 and through diode 20 to input pins 14 of chip 10 during insertion. For example, buffer 88 on backplane board 92 can drive +5 volts to input pin 14 during insertion of removable board 94, while ground bus 44 is below ground, due to coupling of xe2x88x9248 volts through capacitances, and inductances 82.
During insertion, before common ground pin 103 is connected, voltages on input pins 14 have reached 30 volts, with currents of 100 mA. However, diode 20 can burn out with only 30 mA at 14.7 volts reverse bias. Thus hot-swap insertion of telecom boards can produce a sufficiently large EOS pulse to burn out ESD protection diode 20 in chip 10. Although diode 20 passes the standard-model ESD tests, and can perform the ESD protection function fairly well without being damaged, it fails in real-world telecom applications.
During hot insertion, if the connector ground pin 103 connects to backplane bus connector 90 before the signal pin 104 connects, the EOS pulse leaked from power supply 85 through parasitic resistances, capacitances, and inductances 82 can flow through ground pin 103 before it causes damage. Otherwise if signal pin 104 is connected to connector 90 before ground pin 103, the EOS pulse may damage diode 20.
What is desired is additional protection against such EOS pulses seen in hot-swap telecom/datacom applications. Since re-design of chip 10 is difficult, and such telecom hot-swap failures are rare, an external circuit is desired for EOS protection for such applications. An external protection circuit is desired to protect the internal ESD protection diode from failure during hot-swap board insertion.